1. Field of the Invention
The present invention relates to a charge transfer device, particularly to a charge transfer device for converting a signal electric charge to a signal electric potential by means of a floating capacitor.
2. Description of the Prior Art
A prior art charge transfer device is illustrated in FIG. 1 by way of a longitudinal section. This device is an example of a buried channel type two-phase driven type device and is constituted by a p-type silicon substrate 1, an n-type impurity layer 2 formed thereon, first layer charge transfer electrodes 4a, 4b and 4c consisting of polycrystal silicon, second layer charge transfer electrodes 5a and 5b consisting of polycrystal silicon, an insulating film 3 formed between the silicon substrate and the first and the second layer charge transfer electrodes and also between the first layer charge transfer electrodes and the second layer charge transfer electrodes, n.sup.- -type impurity regions 6 formed in surface regions of the n-type impurity layer 2, an output gate 7, a floating capacitor 8 for converting a transferred signal charge to a potential variation, a reset gate 9, an n.sup.+ -type impurity region 10 formed in a surface region of the n-type impurity layer 2 and an output transistor 11 for detecting the potential variation in the floating capacitor 8.
The first layer charge transfer electrodes 4a, 4b and so on are coupled with the left side neighboring second layer charge transfer electrodes 5a, 5b and so on, and to these couples, transfer clock signals .phi..sub.1 and .phi..sub.2 of reverse phases to each other are applied alternately. Further, a fixed output gate 7, a rest pulse .phi..sub.R is applied to the reset gate 9 and a source voltage V.sub.2 is applied to the n.sup.+ -type impurity region 10 and a drain terminal of the output transistor 11.
Next, operation of the prior art device shown in FIG. 1 will be explained with reference to a potential graphs illustrated in FIG. 2.
When the rest pulse .phi..sub.R goes to a high level, a potential of a portion of the n-type impurity layer 2 located between the output gate 7 and the reset gate 9 is set at the source voltage V.sub.2. Then, when the reset pulse .phi..sub.R goes to a low level, said portion of the n-type impurity layer 2, which forms one of the electrodes of the floating capacitor 8, is electrically isolated from other portions. At this time, the transfer clock signal .phi..sub.1 and .phi..sub.2 are set at a high level and a low level, respectively and thus signal charge is stored under the first layer charge transfer electrodes 4a, 4c and so on to which the transfer clock signal .phi..sub.1 is applied [FIG. 2(a)]. Next, when the transfer clock signals .phi..sub.1 and .phi..sub.2 go to a low level and a high level, respectively, the signal charge stored under the charge transfer electrodes to which the trnsfer clock signal .phi..sub.1 is applied is transferred to portions under right-side neighboring charge transfer electrodes to which the transfer clock signal .phi..sub.2 is applied. At this time, the signal charge stored under the final charge transfer electrode 4a flows into the floating capacitor 8 through a channel under the output gate 7 [FIG. 2(b)].
When the transferred signal charge quantity is represented by Q and the capacitance of the floating capacitor is represented by C, potential variation amount .DELTA.V of the floating capacitor 8 can be represented as follows: EQU .DELTA.V=Q/C
This potential variation amount .DELTA.V is taken out through the output transistor 11.
In such a prior art charge transfer device, however, the output voltage value corresponding to the signal charge quantity is decided by the capacitance of the floating capacitor. Therefore, the level of the output voltage corresponding to a fixed signal charge quantity is elevated as the capacitance of the floating diffusion layer is made smaller. For this reason, in order to raise the sensitivity of the charge transfer device, it has been usually employed to reduce the surface area of the floating capacitor, that is, to narrow the distance between the output gate 7 and the reset gate 9 thereby to narrow the distance between channel stoppers existent at both ends of the n-type impurity layer 2. In these days, however, reduction of the capacitance by such means has been achieved to an almost maximum extent and so there is a demand for new means for capacitance reduction in place thereof.